Improved structure for efficient charge recovery logic

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Improved structure for efficient charge recovery logic

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An improved structure for efficient charge recovery logic (IECRL) with better power performance than ECRL coupled with an improved output waveform is presented. At 25 MHz and Vdd = 5 V, the power dissipation of IECRL is ~60% that of the ECRL circuit. HSPICE simulations also show that the voltage can be scaled down to 1.5 V Vdd and that the power saving is further improved. At 25 MHz and Vdd = 1.5 V, the power dissipation of the IECRL circuit is ~ 49% that of the ECRL circuit.

Inspec keywords: logic design; CMOS logic circuits

Other keywords: charge recovery logic; HSPICE simulation; power dissipation reduction; 25 MHz; 1.5 to 5 V

Subjects: Logic and switching circuits; Logic design methods; CMOS integrated circuits; Logic circuits

References

    1. 1)
      • C.C. Yeh , J.H. Lou , J.B. Kuo . 1.5 V CMOS full-swing energy efficientlogic (EEL) circuit suitable for low-voltage and low-power VLSI applications. Electron. Lett. , 16 , 1375 - 1376
    2. 2)
      • Y. Moon , D.K. Jeong . An efficient charge recovery logic circuit. IEEE J. Solid-State Circuits , 4 , 514 - 522
    3. 3)
      • K.T. Lau , F. Liu . Improved adiabatic pseudo-domino logic family. Electron. Lett. , 25 , 2113 - 2114
    4. 4)
      • K.T. Lau , F. Liu . Four-phase improved adiabatic pseudo-domino logic. Electron. Lett. , 4 , 343 - 344
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19981210
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