Boosted charge transfer preamplifier for low power Gbit-scale DRAM

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Boosted charge transfer preamplifier for low power Gbit-scale DRAM

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A new charge transfer preamplifier scheme is developed for low power and high density DRAMs. It employs a boosting method with a MOSFET capacitor for a high voltage precharge level and a pulse control signal for a charge transfer switch. The new scheme increases the sensing margin and enhances the sensing speed under 1.5 V operation with a small area overhead. It also leads to a wider design window for a charge transfer switch as the supply voltage scales down.

Inspec keywords: VLSI; DRAM chips; preamplifiers; MOS memory circuits

Other keywords: high density DRAMs; low power Gbit-scale DRAM; high voltage precharge level; sensing margin improvement; boosted charge transfer preamplifier; sensing speed enhancement; 1.5 V; charge transfer switch; MOSFET capacitor; pulse control signal

Subjects: Semiconductor storage; Memory circuits; Other MOS integrated circuits; Amplifiers

References

    1. 1)
      • J.S. Kim , Y.S. Choi , H.J. Yoo , K.S. Seo . A low noise folded bit-line sensing architecture for multi-GbDRAM with ultra high density 6F2 cell. IEEE J. Solid-State Circuits , 7 , 1096 - 1102
    2. 2)
      • Tsukude, M., Kuge, S., Fujino, T., Arimoto, K.: `A 1.2 V to 3.3 V wide-voltage-range DRAM with0.8 V array operation', ISSCC Dig. Tech. Papers, 1997, p. 66–67.
    3. 3)
      • Itoh, K., Nakagome, Y., Kimura, S., Watanabe, T.: `Limitations and challenges of multi-gigabitDRAM circuits', IEEE Symp. VLSI Circuits Dig. Tech. Papers, 1996, p. 2–7.
    4. 4)
      • Heller, L.G.: `Cross-coupled charge-transfer sense amplifier', ISSCC Dig. Tech. Papers, 1979, p. 20–21.
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