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Modulo address generators for DSPs

Modulo address generators for DSPs

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Digital signal processors implement modulo addressing by using separate hardware generation and comparison. To simplify hardware, they restrict the starting address, the displacement value, and/or the buffer length. The authors show that, by rewriting the equations for modulo addressing, it is possible to combine address generation and comparison to simplify hardware without loss in speed.

Inspec keywords: digital signal processing chips; buffer storage; shift registers; adders

Other keywords: displacement value; circular buffer; registers; buffer length; separate hardware generation/comparison; modulo address generators; high-speed implementation; starting address; digital signal processors; adder

Subjects: Microprocessors and microcomputers; Logic and switching circuits; Semiconductor storage; Memory circuits; Digital signal processing chips; Logic circuits

References

    1. 1)
      • Lucent Technologies, `DSP1628 datasheet', February 1997.
    2. 2)
      • Analog Devices, `ADSP-21020 User's Manual', 1997.
    3. 3)
      • Motorola, `DSP56302 User's Manual', 1997.
    4. 4)
      • R.J. Higgins . (1990) Digital signal processing in VLSI.
    5. 5)
      • Garde, D.: `Apparatus for generating target addresses within a circular buffer includinga register for storing position and size of the circular buffer', US, 5,623,621, 22 April 1997.
    6. 6)
      • Prasad, M.K., Kolagotla, R.K.: `True modulo address generators for digital signal processors', Proc. 8th Intl. Conf. Signal Processing Applications and Technology, September 1997, p. 843–846.
    7. 7)
      • Texas Instruments, `TMS320C62XX Reference Guide', 1997.
    8. 8)
      • Kolagotla, R.K. and Prasad, M.K.: ‘True modulo addressinggenerator’.Patent Application.
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