Multiple twisted data line technique for scaled DRAMs

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Multiple twisted data line technique for scaled DRAMs

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Published

A new multiple twisted data line technique to reduce both bit-line and word-line coupling noises is proposed and demonstrated. An improved noise/signal ratio resulting from the application of the proposed technique is confirmed by soft-error rate tests. A faster data access time can also be expected when the proposed technique is incorporated into dynamic random access memories.

Inspec keywords: integrated circuit noise; DRAM chips

Other keywords: noise/signal ratio; multiple twisted data line; word-line coupling noise; soft-error rate; scaled DRAM; data access time; bit-line coupling noise; dynamic random access memory

Subjects: Memory circuits; Semiconductor storage

References

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      • T. Sakata , M. Horiguchi , T. Sekiguchi , S. Ueda , H. Tanaka , Y. Nakagome , E. Takeda . An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid-State Circuits , 11 , 1165 - 1173
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      • D.-S. Min , D.W. Langer . Twisted bit-line technique for multi-gigabit DRAMs. Electron. Lett. , 16 , 1380 - 1382
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      • H. Hidaka , K. Fujishima , Y. Matsuda , M. Asakura , T. Yoshihara . Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid-State Circuits , 1 , 21 - 27
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      • J.-H. Yoo , C.-H. Kim , K.-H. Kyung , S.-M. Yoo , J.-H. Lee , H.-K. Lim . A 32-bank 1 Gb self-strobing synchronous DRAM with 1 Gbytes/s bandwidth. IEEE J. Solid-State Circuits , 11 , 1635 - 1644
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