http://iet.metastore.ingenta.com
1887

Multiple twisted data line technique for scaled DRAMs

Multiple twisted data line technique for scaled DRAMs

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new multiple twisted data line technique to reduce both bit-line and word-line coupling noises is proposed and demonstrated. An improved noise/signal ratio resulting from the application of the proposed technique is confirmed by soft-error rate tests. A faster data access time can also be expected when the proposed technique is incorporated into dynamic random access memories.

References

    1. 1)
      • D.-S. Min , D.W. Langer . Twisted bit-line technique for multi-gigabit DRAMs. Electron. Lett. , 16 , 1380 - 1382
    2. 2)
      • H. Hidaka , K. Fujishima , Y. Matsuda , M. Asakura , T. Yoshihara . Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid-State Circuits , 1 , 21 - 27
    3. 3)
      • M. Aoki , S. Ikenaga , Y. Nakagome , M. Horiguchi , Y. Kawase , Y. Kawamoto , K. Itoh . New DRAM noise generation under half-Vcc precharge and its reductionusing a transposed amplifier. IEEE J. Solid-State Circuits , 4 , 889 - 894
    4. 4)
      • T. Sakata , M. Horiguchi , T. Sekiguchi , S. Ueda , H. Tanaka , Y. Nakagome , E. Takeda . An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid-State Circuits , 11 , 1165 - 1173
    5. 5)
      • J.-H. Yoo , C.-H. Kim , K.-H. Kyung , S.-M. Yoo , J.-H. Lee , H.-K. Lim . A 32-bank 1 Gb self-strobing synchronous DRAM with 1 Gbytes/s bandwidth. IEEE J. Solid-State Circuits , 11 , 1635 - 1644
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19980933
Loading

Related content

content/journals/10.1049/el_19980933
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address