Modified Booth pipelined multiplication

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Modified Booth pipelined multiplication

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A pipelined modified Booth multiplication is proposed for low power, high performance DSP application. The proposed multiplication is suitable for VLSI implementation. It has a better power-performance ratio than the traditional pipelined multiplier and modified Booth multiplier.

Inspec keywords: multiplying circuits; pipeline arithmetic; VLSI; digital signal processing chips

Other keywords: pipelined modified Booth multiplication; low power DSP; VLSI; power-performance ratio

Subjects: Logic circuits; Microprocessors and microcomputers; Digital arithmetic methods; Parallel architecture; Digital signal processing chips

References

    1. 1)
      • A.P. Chandrakasan , S. Sheng , R.W. Brodersen . Low power CMOS digital design. IEEE J. Solid-State Circuits , 4 , 473 - 484
    2. 2)
      • A.D. Booth . A signed binary multiplication technique. Q. J. Mech. Appl. Math. , 2 , 236 - 240
    3. 3)
      • M.S. Elrabaa , I.S. Abu-Khater , M.I Elmasry . (1997) Advanced low-power digital circuit techniques.
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