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Statistical power estimation of CMOS logic circuits with variable errors

Statistical power estimation of CMOS logic circuits with variable errors

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  • Author(s): Y.H. Park 1  and  E.S. Park 2
    • View affiliations
    • Affiliations: 1: Electronics and Telecommunications Research Institute (ETRI), Taejon, Korea
      2: Department of Electronic Engineering, Hanyang University, Kyunggido, Korea
  • Source: Volume 34, Issue 11, 28 May 1998, p. 1054 – 1056
    DOI:  10.1049/el:19980801 , Print ISSN 0013-5194, Online ISSN 1350-911X
© IEE
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A statistical power estimation method is proposed where estimation time and accuracy can be balanced by assigning smaller (higher) errors to the nodes with higher (lower) power dissipation. To determine the errors, a quadratic programming based problem is formulated. Experimental results show a drastic reduction in the number of simulation patterns, compared to previous methods.

Inspec keywords: estimation theory; CMOS logic circuits; circuit analysis computing; quadratic programming; statistical analysis; error analysis; iterative methods

Other keywords: estimation accuracy; power dissipation; quadratic programming based problem; estimation time; variable errors; CMOS logic circuits; statistical power estimation

Subjects: Logic and switching circuits; Optimisation; Interpolation and function approximation (numerical analysis); Statistics; Computer-aided circuit analysis and design; CMOS integrated circuits; Optimisation techniques; Electronic engineering computing; Other topics in statistics; Optimisation techniques; Error analysis in numerical methods; Numerical analysis; Other topics in statistics; Logic circuits; Error analysis in numerical methods; Interpolation and function approximation (numerical analysis)

References

    1. 1)
      • Cirit, M.A.: `Estimating dynamic power consumption of CMOS circuits', IEEE Proc. Int. Conf.Computer Aided Design, 1987, p. 534–537.
    2. 2)
      • Brglez, F., Fujiwara, H.: `A neutral netlist of 10 combinational benchmark circuits and a targettranslator in fortran', IEEE International Symp. on Circuits and Systems, 1985, p. 695–698.
    3. 3)
      • Xakellis, M., Najm, F.N.: `Statistical estimation of the switching activity in digital circuits', ACM/IEEE Proc. Design Automation Conf., 1994, p. 728–733.
    4. 4)
      • R. Burch , F.N. Najm , P. Yang , T. Trick . A Monte Carlo approach for power estimation. IEEETrans. Very Large Scale Integr. Syst. , 1 , 63 - 71
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