Statistical power estimation of CMOS logic circuits with variable errors

Statistical power estimation of CMOS logic circuits with variable errors

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A statistical power estimation method is proposed where estimation time and accuracy can be balanced by assigning smaller (higher) errors to the nodes with higher (lower) power dissipation. To determine the errors, a quadratic programming based problem is formulated. Experimental results show a drastic reduction in the number of simulation patterns, compared to previous methods.


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