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CMOS dynamic ternary circuit with full logic swing and zero-static power consumption

CMOS dynamic ternary circuit with full logic swing and zero-static power consumption

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Published

A new dynamic circuit scheme to realise ternary logic is presented. The main properties are the use of the standard CMOS process without any modification of the thresholds, the minimum possible number of external voltage levels (three), the highest possible logic swing and noise margins and the absence of static power consumption.

Inspec keywords: logic design; ternary logic; logic gates; multivalued logic circuits; CMOS logic circuits

Other keywords: ternary inverter; ternary logic; standard CMOS process; CMOS dynamic ternary circuit; zero-static power consumption; full logic swing; noise margins

Subjects: Logic circuits; Logic design methods; CMOS integrated circuits; Logic and switching circuits; Semiconductor logic elements

References

    1. 1)
      • K.W. Current . Current-mode CMOS multiple-valued logic circuits. IEEE J. Solid-State Circuits , 2 , 95 - 107
    2. 2)
      • A. Herrfeld , S. Hentschke . CMOS ternary dynamic differential logic. Electron. Lett. , 10 , 762 - 763
    3. 3)
      • M. Yoeli , G. Rosenfeld . Logical design of ternary switching circuits. IEEE Trans. Electronic Comput. , 19 - 29
    4. 4)
      • C.-Y. Wu , H.-H. Huang . Design and application of pipelined dynamic CMOS ternary logic and simpleternary differential logic. IEEE J. Solid-State Circuits , 8 , 895 - 906
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