Gate-controlled double electron layer tunnelling transistor and single transistor digital logic applications

Gate-controlled double electron layer tunnelling transistor and single transistor digital logic applications

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A novel entirely planar quantum transistor based on tunnelling between two separate electron layers in an AlGaAs/GaAs double quantum well heterostructure is demonstrated. Using the gate-tunability of the tunnelling I-V characteristics, digital logic gates such as XOR and NAND are demonstrated using a single double electron layer tunnelling transistor.


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