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Area-efficient architectures for integrated N-port memories employ blocks of one port memory cells and dynamic port-to-block connections. The authors determine the block number M necessary to achieve a target port-access-rejection probability for a given port number N and best-case/worst-case conflict-resolve algorithms, by applying stochastic probability theory.
Inspec keywords: circuit optimisation; memory architecture; stochastic processes; multiport networks; cellular arrays; probability
Other keywords:
Subjects: Other topics in statistics; Memory circuits; Semiconductor storage; Other topics in statistics