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Pass-transistor adiabatic logic with NMOS pull-down configuration

Pass-transistor adiabatic logic with NMOS pull-down configuration

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A new low power adiabatic logic family, pass-transistor adiabatic logic with NMOS pull-down configuration, is presented. For a 2:1 multiplexer, a power saving of ~80% is achieved, compared to a 2N-2N2P logic circuit at 20 MHz. Compared to pass-transistor adiabatic logic using single power-clock supply (PAL), the ‘tri-state’ problem is solved, while power consumption is comparable. A four phase sinusoidal clock power supply is employed in the new logic family, which facilitates pipelining hence leading to higher throughput, compared to PAL.

Inspec keywords: timing; CMOS logic circuits

Other keywords: pipelining; 20 MHz; multiplexer; NMOS pull-down configuration; four phase sinusoidal clock power supply; tri-state problem; power consumption; pass-transistor adiabatic logic; low power adiabatic logic family

Subjects: Logic circuits; CMOS integrated circuits; Logic and switching circuits

References

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