Sign extension bit minimisation algorithm for designing VLSI inner-product-processor cells for DSP applications

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Sign extension bit minimisation algorithm for designing VLSI inner-product-processor cells for DSP applications

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A new sign extension bit minimisation algorithm is presented to design efficient inner-product-processor cells with reduced area and computation time. Design examples are presented for the sake of illustration.

Inspec keywords: digital signal processing chips; digital arithmetic; minimisation; VLSI

Other keywords: sign extension bit minimisation algorithm; inner-product-processor cells; DSP applications; VLSI

Subjects: Microprocessors and microcomputers; Digital signal processing chips; Digital arithmetic methods; Optimisation techniques; Optimisation techniques

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