Forward body-bias SRAM circuitry on bulk Si with twin double-well

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Forward body-bias SRAM circuitry on bulk Si with twin double-well

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A novel SRAM cell suitable for low-voltage adiabatic logic is proposed. This cell uses forward body-bias effects, which are controlled by the stored data, to prevent a passgate transistor from turning on when a large source-to-drain voltage exists.

Inspec keywords: memory architecture; SRAM chips; CMOS memory circuits; silicon

Other keywords: Si; static RAM; forward body-bias effects; SRAM circuitry; low-voltage adiabatic logic; twin double-well; bulk Si

Subjects: Memory circuits; Semiconductor storage; CMOS integrated circuits

References

    1. 1)
      • Kotaki, H., Kakimoto, S., Matsuoka, T., Adachi, K., Sugimoto, K., Fukushima, T., Sato, Y.: `Novel bulk dynamic threshold voltage MOSFET(B-DTMOS) with advanced isolation (SITOS) and gate to shallow-wellcontact (SSS-C) process for ultra low power dual gate CMOS', Tech. Dig.1996 Int. Electron Device Meeting, 1996, p. 459–462.
    2. 2)
      • R. Landauer . Irreversibility and heat generation in the computing process. IBM J. Res. Dev. , 183 - 191
    3. 3)
      • Assaderaghi, F., Sinitsky, D., Parke, S., Bokor, J., Ko, P.K., Hu, C.: `A dynamic threshold voltage MOSFET (DTMOS) for ultra-lowvoltage operation', Tech. Dig. 1994 Int. Electron Device Meeting, 1994, p. 809–812.
    4. 4)
      • Tzartzanis, N., Athas, W.C.: `Energy recovery for the design of high-speed, low-power static RAMs', Dig. Tech. Papers ISLPED96, Aug. 1996, Monterey, CA, p. 55–60.
    5. 5)
      • K. Kioi , H. Kotaki , S. Kakimoto , T. Fukushima , Y. Sato . Forward body-bias MOS (FBMOS) dual rail logic using an adiabatic charging technique with sub-0.6 V operation. Electron. Lett. , 14 , 1200 - 1201
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