Advances in VLSI technology have rendered the implementation of complex operation sequences or transactions inside the body of hardware memory chips a concrete possibility. We show that such an implementation will provide an attractive performance gain and demonstrate the effectiveness through simulation.
References
-
-
1)
-
Asthana, A., Cravatts, M., Krzyzanowski, P.: `An experimental active-memory-basednetwork element', Proc. Third Int. Symp. High-PerformanceDistributed Comput., 1994, IEEE, p. 139–148.
-
2)
-
P.A. Bernstein ,
V. Hadzilacos ,
N. Goodman
.
(1987)
Concurrency control and recovery indatabase systems.
-
3)
-
Herlihy, M.P., Moss, J.E.B.: `Transactional memory: Architectural supportfor lock-free data structure', Proc. 20th Ann. Int. Symp. Computer Architecture, 1993, IEEE, p. 289–300.
-
4)
-
Microelectronics and ComputerTechnol. Corporation, Schwetman, H.: `CSIM reference manual (Revision 17)', .
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19971003
Related content
content/journals/10.1049/el_19971003
pub_keyword,iet_inspecKeyword,pub_concept
6
6