Twisted bit-line technique for multi-gigabit DRAMs

Twisted bit-line technique for multi-gigabit DRAMs

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A new twisted bit-line (TBL) technique is presented to reduce bit-line coupling noise for multi-gigabit DRAMs. Sufficient noise reduction effects have been monitored through soft-error rate measurement on test chips using the proposed TBL technique. Also, the problem of excessive chip area penalty in the conventional TBL techniques can be solved in the proposed TBL technique.


    1. 1)
      • J.-H. Yoo , C.-H. Kim , K.-C. Lee , K.-H. Kyung , S.-M. Yoo , J.-H. Lee , M.-H. Son , J.-M. Han , J.-W. Park , H.-K. Lim . A 32-bank 1 Gb self-strobing synchronous DRAM with 1 Gbytes/s bandwidth. IEEE J. Solid-State Circuits , 11
    2. 2)
      • Nitta, Y., Sakashita, N., Shimomura, K., Okuda, F., Shimano, H., Yamakawa, S., Furukawa, A., Abe, H.: `A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture', ISSCC 96, Dig. Tech. Papers, February 1996, p. 376–377.
    3. 3)
      • H. Hidaka , K. Fujishima , Y. Matsuda , M. Asakura , T. Yoshihara . Twisted bit-line architectures for multi-megabit DRAMs. IEEE J. Solid-State Circuits , 1 , 21 - 27
    4. 4)
      • M. Aoki , S. Ikenaga , Y. Nakagome , M. Horiguchi , Y. Kawase , Y. Kawamoto , K. Itoh . New DRAM noise generation under half-Vcc precharge and its reductionusing a transposed amplifier. IEEE J. Solid-State Circuits , 4 , 889 - 893
    5. 5)
      • K. Tsuchida , Y. Oowaki , M. Ohta , D. Takashima , S. Watanabe , K. Ohuchi , F. Masuoka . The stabilised reference-line technique for scaled DRAMs. IEEE J. Solid-State Circuits , 1 , 24 - 29

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