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Use of current sensing technique in designing asynchronous static RAM for self-timed systems

Use of current sensing technique in designing asynchronous static RAM for self-timed systems

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The conventional static RAM was modified so that it can communicate with other self-timed systems. The four-phase handshake control protocol was used and the current-sensing completion detection (CSCD) technique was studied for the read completion signal generation. The authors present the implementation and simulation results of a test circuit.

Inspec keywords: memory protocols; asynchronous circuits; SRAM chips

Other keywords: circuit simulation; read completion signal generation; four-phase handshake control protocol; current-sensing completion detection; self-timed system; asynchronous static RAM design

Subjects: Semiconductor storage; Memory circuits

References

    1. 1)
      • Seevinck, E.: `A current sense-amplifier for fast CMOS SRAMs', IEEE Symp. VLSI Circuits, 1990, p. 71–72.
    2. 2)
      • P.Y. Chee , P.C. Liu , L. Siek . High-speed hybrid current-mode sense amplifier for CMOS SRAMs. Electron. Lett. , 9 , 871 - 873
    3. 3)
      • Furber, S.B., Day, P.: `Four-phase micropipeline latch control circuits', , , 1994.
    4. 4)
      • Dean, M.E., Dill, D.L., Horowitz, M.: `Self-timed logic using current-sensing completion detection (CSCD)', , , 1991.
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