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Double-edge-triggered address pointer for low-power high-speed FIFO memories

Double-edge-triggered address pointer for low-power high-speed FIFO memories

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The clock line, which is used to shift the addresses in the address pointer circuit of an FIFO, has a large load capacitance and hence large power consumption is required to drive the line. Furthermore, the large load capacitance limits the speed of operation of the FIFO. The authors develop a double-edge-triggered technique for address pointer design. By using the proposed technique, the high-speed FIFO operation can be realised with relatively lower shift clock frequency. The power consumption of the new circuit is significantly reduced due to the reduction of the shifting clock frequency as well as the cumulative load capacitance on shifting clock lines.

References

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      • A. Mukherjee . (1986) nMOS and CMOS VLSI systems design.
    2. 2)
      • M. Shoji . (1987) CMOS digital circuit technology.
    3. 3)
      • M. Hashimoto , M. Nomura . A 20-ns 256K×4 FIFO memory. IEEE J. Solid-State Circuits , 2 , 490 - 499
    4. 4)
      • R. Hossain , L.D. Wronski , A. Albicki . Low power design using double edge triggered flip-flop. IEEE Trans. VLSI Syst. , 2 , 261 - 265
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