Harmonic distortion due to output conductance in SI cells

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Harmonic distortion due to output conductance in SI cells

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A closed-form equation for the effect of the output conductance on the harmonic distortion in switched-current basic memory cells is presented here. The authors show that in memory cells with short channel transistors, the variation of the output conductance can generate high levels of harmonic distortion (–51 dB for L = 2 µm using a 1.2 µm CMOS technology); however a suitable relation of transistor lengths can lead to very low distortion levels. The results are confirmed both by simulation and measurements on an IC prototype.

Inspec keywords: CMOS analogue integrated circuits; analogue storage; harmonic distortion; CMOS memory circuits; switched current circuits

Other keywords: output conductance; SI cell; short channel transistor; switched-current memory cell; CMOS technology; IC; 1.2 micron; harmonic distortion

Subjects: CMOS integrated circuits; Time varying and switched networks; Analogue processing circuits

References

    1. 1)
      • Yang, H.: `Current-feedthrough effects and cancellation techniques in switched-currentcircuits', ISCAS'90, p. 3186–3188.
    2. 2)
      • Hughes, J.: `Switched-currents, a new technique for analog sample-data signal processing', ISCAS'89, p. 1584–1587.
    3. 3)
      • P. Crawley , G. Roberts . Predicting harmonic distortion in switched-current memory circuits. IEEE Trans. Circuits Systems-II , 2 , 73 - 86
    4. 4)
      • Hughes, J., Macbeth, I., Pattullo, D.: `Second generation switched-current signal processing', ISCAS'90, p. 2805–2808.
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