Design of a Viterbi decoder with low power using minimum-transition traceback scheme

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Design of a Viterbi decoder with low power using minimum-transition traceback scheme

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The authors propose a novel traceback scheme for the implementation of a low power Viterbi decoder. With minor modification of a conventional traceback scheme, the memory access count needed to perform the traceback function can be reduced by a factor of ~5.0–10.0 over the conventional traceback scheme. Experimental results confirm the efficiency of the proposed scheme.

Inspec keywords: Viterbi decoding; CMOS digital integrated circuits; high definition television

Other keywords: Viterbi decoder; HDTV receiver; minimum-transition traceback scheme; low power operation

Subjects: Other digital circuits; High definition television and video; CMOS integrated circuits; Codes

References

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      • Tsui, , Pedram, M., Despain, A.: `Exact and approximate methods for switching activity estimation in sequentiallogic circuits', Proc. 31st DAC, June 1994, p. 18–23.
    2. 2)
      • `ATSC digital television standard', A/53, 1995.
    3. 3)
      • Oh , Kim , Hwang . A VLSI architecture of the trellis decoder block for the digital HDTVgrand alliance system. IEEE Trans. Consum. Electron. , 3 , 346 - 356
    4. 4)
      • J.A. Heller , I.M. Jacobs . Viterbi decoding for satellite and space communication. IEEE Trans. Commun. Technol. , 5 , 835 - 848
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