Gallium arsenide pseudo-dynamic latched logic

Access Full Text

Gallium arsenide pseudo-dynamic latched logic

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A new GaAs logic family, pseudo-dynamic latched logic (PDLL), is introduced. Compared with traditional static GaAs logic families, PDLL allows complex gate design with less power dissipation. In addition, it overcomes problems associated with charge degradation in the storage nodes in dynamic logic gates, and operates at relatively high temperatures. PDLL is self-latched which leads to the possibility of implementing compact pipeline systems.

Inspec keywords: pipeline processing; gallium arsenide; integrated circuit noise; field effect logic circuits; III-V semiconductors; integrated circuit design; logic gates

Other keywords: self-latched; GaAs; complex gate design; power dissipation; storage nodes; pseudo-dynamic latched logic; charge degradation; compact pipeline systems; PDLL; logic families

Subjects: Other field effect integrated circuits; Logic circuits

References

    1. 1)
      • P.S. Lassen , S.I. Long , K.R. Nary . Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic. IEEE J. Solid-State Circuits , 10 , 1038 - 1045
    2. 2)
      • R. Sarmiento , P.P. Carballo , A. Núñez . High speed primitives of hardware accelerators for DSP in GaAs technology. IEE Proc. G , 2 , 205 - 216
    3. 3)
      • D.H.K. Hoe , C.A.T. Salama . GaAs trickle transistor dynamic logic. IEEE J. Solid-State Circuits , 10 , 1441 - 1448
    4. 4)
      • L. Yang , R. Chakharapani , S.I. Long . A high-speed dynamic domino circuit implemented with GaAs MESFETs. IEEE J. Solid-State Circuits , 874 - 879
    5. 5)
      • K. Eshraghian , R. Sarmiento , P.P. Carballo , A. Núñez . Speed-area-power optimization for DCFL and SDCFL class of logic usingring notation. Microprocess. Microprog. , 75 - 82
    6. 6)
      • D.H.K. Hoe , C.A.T. Salama . Dynamic GaAs capacitively coupled domino logic (CCDL). IEEE J. Solid-State Circuits , 6 , 874 - 879
    7. 7)
      • O.M.K. Law , C.A.T. Salama . GaAs split phase dynamic logic. IEEE J. Solid-State Circuits , 5 , 627 - 622
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960926
Loading

Related content

content/journals/10.1049/el_19960926
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading