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Low power dual-port CMOS SRAM macro design

Low power dual-port CMOS SRAM macro design

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Published

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 µm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers.

Inspec keywords: SRAM chips; circuit analysis computing; CMOS memory circuits; SPICE; two-port networks

Other keywords: FIFO buffers; 2 to 5 V; supply voltage; dual-port CMOS SRAM; macro design; current-mode signal transmission; current-mode sense amplifier; HSPICE simulations; 0.5 micron; low power advantage

Subjects: Computer-aided circuit analysis and design; Memory circuits; CMOS integrated circuits; Semiconductor storage; Electronic engineering computing

References

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