Low power dual-port CMOS SRAM macro design

Access Full Text

Low power dual-port CMOS SRAM macro design

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 µm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers.

Inspec keywords: SRAM chips; circuit analysis computing; CMOS memory circuits; SPICE; two-port networks

Other keywords: FIFO buffers; 2 to 5 V; supply voltage; dual-port CMOS SRAM; macro design; current-mode signal transmission; current-mode sense amplifier; HSPICE simulations; 0.5 micron; low power advantage

Subjects: Computer-aided circuit analysis and design; Memory circuits; CMOS integrated circuits; Semiconductor storage; Electronic engineering computing

References

    1. 1)
      • E. Seevinck , P. Beers , H. Ontrop . Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOSSRAM's. IEEE J. Solid-State Circuits , 4 , 525 - 536
    2. 2)
      • B. Chappel , S. Schuster , G. Sai-Halasz . Stability and SER analysis ofstatic RAM cells. IEEE J. Solid-State Circuits , 1 , 383 - 390
    3. 3)
      • E. Seevinck , F. List , J. Lohstroh . Static-noise margin analysis of MOSSRAM cells. IEEE J. Solid-State Circuits , 5 , 748 - 754
    4. 4)
      • N. Tan , S. Erikson . Low-power chip-to-chip communication circuits. Electron. Lett. , 21 , 1732 - 1733
    5. 5)
      • T.N. Blalock , R.C. Jaeger . A high-speed clamped bit-line current-mode sense amplifier. IEEE J. Solid- State Circuits , 4 , 542 - 548
    6. 6)
      • N.H. Weste , K. Eshraghian . (1985) Principles of CMOS VLSI design, Asystems perspective.
    7. 7)
      • B. Prince . (1991) Semiconductor memories, A handbook of design, manufactureand application.
    8. 8)
      • P.Y. Chee , P.C. Liu , L. Siek . High-speed hybrid current-mode sense amplifier for CMOS SRAMs. Electron. Lett. , 9 , 871 - 873
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960907
Loading

Related content

content/journals/10.1049/el_19960907
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading