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Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design

Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design

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The authors present a novel algorithm for area minimisation in digital signal processing ASIC design. After determining the optimised fixed point representation for each signal, the proposed algorithm divides abstract operations in design description into partitions so that operations in the same partition can share a hardware module. Experimental results show the efficacy of the proposed algorithm by generating the DSP hardwares requiring smaller area under given performance constraints.

References

    1. 1)
      • Kum, K., Sung, W.: `VHDL based fixed point digital signal processing algorithm developmentsoftware', Proc. Int. Conf. VLSI and CAD, Nov. 1993, Seoul, Korea, p. 257-260
    2. 2)
      • Digital Signal Processing in VLSI
    3. 3)
      • The high level synthesis of digital systems
    4. 4)
      • An optimal scheduling method based upon the lower bound cost estimation(high level synthesis)
    5. 5)
      • An efficient heuristic procedure for partitioning graphs
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