http://iet.metastore.ingenta.com
1887

Sub-quarter-micrometre GaAs MESFET process with WSi sidewall gate

Sub-quarter-micrometre GaAs MESFET process with WSi sidewall gate

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors have developed a novel sub-quarter-micrometre WSi sidewall gate GaAs MESFET (SIG-FET) fabrication process. In this process, using WSi sidewalls as gate electrodes, the gate length is controlled only by the thickness of a WSi thin film deposited by sputtering, and sub-quarter-micrometre gates can be fabricated easily without using photolithography. The 0.15 µm-gate SIG-FET has exhibited ft = 50 GHz and fmax = 120 GHz.

References

    1. 1)
      • G.W. Wang , Y.K. Chen , W.J. Schaff , L.F. Eastman . A 0.1-µm gateAl0.5In0.5As/Ga0.5In0.5As MODFET fabricated on GaAs substrates. IEEE Trans. ElectronDevices , 818 - 823
    2. 2)
      • A.N. Lepore , H.M. Levy , R.C. Tiberio , P.J. Tasker , H. Lee , E.D. Wolf , L.F. Eastman , E. Kohn . 0.1 µm gate length MODFETs with unity currentgain cutoff frequency above 110 GHz. Electron. Lett. , 364 - 366
    3. 3)
      • N. Samoto , Y. Makino , K. Onda , E. Mizuki , T. Itoh . A novelelectron-beam exposure technique for 0.1-µm T-shaped gate fabrication. J. Vac. Sci.Technol. B , 1335 - 1338
    4. 4)
      • M. Feng , J. Laskar . On the speed and noise performance of direct ion-implantedGaAs MESFET's. IEEE Trans. Electron Devices , 9 - 17
    5. 5)
      • E.Y. Chang , K.C. Lin , E.H. Liu , C.Y. Chang , T.H. Chen , J. Chen . Submicron T-shaped gate HEMT fabrication using deep-UV lithography. IEEE Electron DeviceLett. , 277 - 279
    6. 6)
      • A. Tamura , Y. Ikeda , T. Yokoyama , K. Inoue . WSiN/SiO2 cappedannealing for Si-implanted GaAs. J. Appl. Phys. , 6171 - 6174
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960657
Loading

Related content

content/journals/10.1049/el_19960657
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address