http://iet.metastore.ingenta.com
1887

Implementation issues of the ATM cell delineation mechansim

Implementation issues of the ATM cell delineation mechansim

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The cell delineation mechanism (CDM) used in the asynchronous transfer mode (ATM) interfaces is based on the validation of the header error control (HEC) byte of the incoming cells, and is used for extracting the boundaries of the incoming cell stream. The CDM is analysed and an efficient implementation algorithm is derived, resulting in a hardware architecture, applicable at high data rates.

References

    1. 1)
      • CCITT I.432 Resolution 2, 1990, B-ISDN User-Network Interface— PhysicalLayer Specification
    2. 2)
      • ATM Forum: ‘Intermediate ATM: SONET cell delineation’Educational package,Release 1.0, August 1994
    3. 3)
      • A SONET STS-3c user networkinterface integrated circuit
    4. 4)
      • High-speed parallel CRC circuits in VLSI
    5. 5)
      • Single-bit error correctioncircuit for ATM interfaces
    6. 6)
      • A tutorial on CRC computations
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960631
Loading

Related content

content/journals/10.1049/el_19960631
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address