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IDDQ test invalidation by break faults

IDDQ test invalidation by break faults

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The effectiveness of IDDQ testing for bridging faults in CMOS ICs can be decreased if break faults are present in the circuit. The robustness to such invalidation is investigated here, leading to claims for a better test pattern generation for IDDQ testing. As for the proposed solution, test vectors that activate a larger number of different current paths can build a more robust test sequence.

Inspec keywords: integrated circuit testing; CMOS integrated circuits; fault diagnosis

Other keywords: quiescent power-supply current monitoring; break faults; test pattern generation; IDDQ testing; bridging faults; CMOS ICs; invalidation robustness

Subjects: Manufacturing processes; Testing; Production facilities and engineering; CMOS integrated circuits

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