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Operation of a single-ended 550 Mbit/s, 41 fJ, hybrid CMOS/MQW receiver-transmitter

Operation of a single-ended 550 Mbit/s, 41 fJ, hybrid CMOS/MQW receiver-transmitter

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A single-ended, asynchronous, transimpedance receiver-transmitter circuit with 5 mW power dissipation, is implemented in 0.8 µm silicon CMOS. A hybrid flip-chip bonding technique is used to attach GaAs-AlGaAs MQW detectors and modulators to the circuit. Operation of the circuit at a sensitivity of –19.4 dBm (41 fJ) and a bit error rate <10-9 at 550 Mbit/s is demonstrated.

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