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Asynchronous VLSI architecture for adaptive echo cancellation

Asynchronous VLSI architecture for adaptive echo cancellation

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A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5 kHz.

Inspec keywords: asynchronous circuits; adaptive filters; pipeline processing; least mean squares methods; VLSI; FIR filters; echo suppression

Other keywords: FIR filter; adaptive echo cancellation; power-of-two modified LMS algorithm; pipelined circuit; filtered output; asynchronous VLSI architecture; sampling rate

Subjects: Interpolation and function approximation (numerical analysis); Digital filters; Digital filters; Electromagnetic compatibility and interference; Interpolation and function approximation (numerical analysis)

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      • W.Y. Chen , J.L. Dixon , D.L. Waring . High bit rate digital subscriber line echo cancellation. IEEE J. Sel. Areas Commun. , 6 , 848 - 860
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      • Cowan, C.F.: `An evaluation of analogue and digital adaptive filter realisations', Intl. SpecialistSeminar on Case Studies in Advanced Signal Processing, Sept. 1979, p. 178–183.
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      • Lu, F., Samueli, H.: `A 60-Mbaud adaptive transversal equalizer in 1.0 µm CMOS for QAMdigitalmodems', Proc. 1993 Custom Integrated Circuits Conf., March 1993, p. 16.6.1–16.6.4.
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