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Relative VLSI costs of WDFs implemented using redundant and non-redundant arithmetic

Relative VLSI costs of WDFs implemented using redundant and non-redundant arithmetic

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The lattice wave digital filter (LTWDF) is known to be especially suitable for high speed filtering applications, owing to the low coefficient wordlengths required. The authors present a comparison between several LTWDF architectures using redundant and non-redundant arithmetic. It is shown that architectures using non-redundant arithmetic require up to 2.5 times less VLSI area, while offering higher sample rates for most practical filtering applications.

Inspec keywords: lattice filters; redundant number systems; VLSI; wave digital filters; digital arithmetic; pipeline arithmetic

Other keywords: WDF architectures; redundant arithmetic; VLSI area; high speed filtering applications; block level pipelining; nonredundant arithmetic; sample rates; lattice WDF; lattice wave digital filter

Subjects: Digital filters; Digital filters; Digital arithmetic methods

References

    1. 1)
      • R.J. Singh , J.V. McCanny . High performance VLSI architectures for wave digital filtering. J. VLSI Signal Process. , 269 - 278
    2. 2)
      • S.S. Lawson , A. Wicks . Design of efficient digital filters satisfying arbitrary loss anddelay specifications. IEE Proc. G , 5 , 611 - 620
    3. 3)
      • S.E. McQuillan , J.V. McCanny . A systematic methodology for the design ofhigh performance recursive digital filters. IEEE Trans. Comput. , 8 , 971 - 982
    4. 4)
      • M. Anderson , S. Summerfield , S. Lawson . Realisation of lattice wave digital filters using three-port adaptors. Electron. Lett. , 8 , 628 - 629
    5. 5)
      • B.P. McGovern , R.F. Woods , C. McAllister . Optimised multiply/accumulate architecture for very high throughput ratedigital filters. Electron. Lett. , 14 , 1135 - 1136
    6. 6)
      • K.K. Parhi , D.G. Messerschmitt . Pipeline interleaving and parallelism in recursivedigital filters - Part II: Pipelined incremental block filtering. IEEE Trans.Acoust., Speech Signal Process. , 7 , 1118 - 1134
    7. 7)
      • Harris-Dowsett, D., Wicks, T., Summerfield, S.: `A pipelining method for high speedVLSI wave digital filters', 37th Midwest Symp. Circuits Syst., August 1994, 2, p. 1091–1094.
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