Asymptotic upper bound for multiplier design
Asymptotic upper bound for multiplier design
- Author(s): R.G.E. Pinch
- DOI: 10.1049/el:19960348
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- Author(s): R.G.E. Pinch 1
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View affiliations
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Affiliations:
1: Department of Pure Mathematics and Mathematical Statistics, University of Cambridge, Cambridge, United Kingdom
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Affiliations:
1: Department of Pure Mathematics and Mathematical Statistics, University of Cambridge, Cambridge, United Kingdom
- Source:
Volume 32, Issue 5,
29 February 1996,
p.
420 – 421
DOI: 10.1049/el:19960348 , Print ISSN 0013-5194, Online ISSN 1350-911X
The cost, in terms of adders/subtractors, of multiplication by n-bit integers when shifts are free is shown to be of the order of n/(log n)α for any α < 1.
Inspec keywords: digital arithmetic; multiplying circuits
Other keywords:
Subjects: Logic circuits; Digital arithmetic methods
References
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- A.G. Dempster , M.D. Macleod . Constant integer multiplication using minimum adders. IEE Proc., Circuits Devices Syst. , 5 , 407 - 413
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- A.G. Dempster , M.D. Macleod . General algorithms for reduced-adder integer multiplier design. Electron. Lett. , 21 , 1800 - 1802
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- Hartley, R.: `Optimization of canonic signed-digit multipliers for circuit design', Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'91), 1991, p. 1992–1995.
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- Potkonjak, M., Srivasta, M.B., Chandrakasan, A.: `Efficient substitution of multiple constant multiplications by shiftsand additions using iterative pairwise matching', Proc. 31st ACM/IEEE Design Automation Conf., 1994, p. 189–194.
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- Y. Han , D. Gollman , C. Mitchell , C. Boyd . (1994) Minimal weight , Cryptography and coding, .
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