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Asymptotic upper bound for multiplier design

Asymptotic upper bound for multiplier design

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The cost, in terms of adders/subtractors, of multiplication by n-bit integers when shifts are free is shown to be of the order of n/(log n)α for any α < 1.

References

    1. 1)
      • A.G. Dempster , M.D. Macleod . Constant integer multiplication using minimum adders. IEE Proc., Circuits Devices Syst. , 5 , 407 - 413
    2. 2)
      • A.G. Dempster , M.D. Macleod . General algorithms for reduced-adder integer multiplier design. Electron. Lett. , 21 , 1800 - 1802
    3. 3)
      • Hartley, R.: `Optimization of canonic signed-digit multipliers for circuit design', Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'91), 1991, p. 1992–1995.
    4. 4)
      • Potkonjak, M., Srivasta, M.B., Chandrakasan, A.: `Efficient substitution of multiple constant multiplications by shiftsand additions using iterative pairwise matching', Proc. 31st ACM/IEEE Design Automation Conf., 1994, p. 189–194.
    5. 5)
      • Y. Han , D. Gollman , C. Mitchell , C. Boyd . (1994) Minimal weight , Cryptography and coding, .
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