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Single-clock-cycle two-dimensional median filter

Single-clock-cycle two-dimensional median filter

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  • Author(s): V.A. Pedroni 1  and  A. Yariv 2
    • View affiliations
    • Affiliations: 1: LAC - Central R&D Laboratory, Centro Politecnico UFPR, Curitiba, Brazil
      2: Electrical Engineering and Applied Physics, California Institute of Technology, Pasadena, USA
  • Source: Volume 32, Issue 5, 29 February 1996, p. 440 – 441
    DOI:  10.1049/el:19960301 , Print ISSN 0013-5194, Online ISSN 1350-911X
© IEE
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Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block.

Inspec keywords: digital signal processing chips; median filters; image processing; two-dimensional digital filters; CMOS digital integrated circuits

Other keywords: 2D median filter; two-dimensional median filter; 2D data block; impulsive noise removal; single-clock-cycle filter; CMOS implementation; image processing

Subjects: Optical information, image and video signal processing; Digital filters; Computer vision and image processing techniques; CMOS integrated circuits; Microprocessors and microcomputers; Digital signal processing chips; Digital filters

References

    1. 1)
      • P. Wendt , E. Coyle , S. Gallagher . Stack filters. IEEE Trans. Acoust. Speech Signal Process. , 898 - 911
    2. 2)
      • O. Yli-Harja , J. Astola , Y. Neuro . Analysis of the properties of median and weighted median filters usingthreshold logic and stack filter representation. IEEE Trans. Signal Process. , 395 - 410
    3. 3)
      • Cauwenberghs, G., Pedroni, V.A.: `A charge-based CMOS parallel analog vector quantizer', Conference on Adv. Neural Inf. Process. Systems (NIPS), 1994, Denver.
    4. 4)
      • Pedroni, V.A.: `VLSI systems for analog and Hamming parallel computation', 1995, PhD thesis, California Institute of Technology.
    5. 5)
      • V.A. Pedroni . Neural n-port voltage comparator network. Electron. Lett. , 1774 - 1775
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