Realising a time-delay neural network on a wavefront toroidal mesh-array neurocomputer

Access Full Text

Realising a time-delay neural network on a wavefront toroidal mesh-array neurocomputer

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors propose a scheme that maps a time-delay neural network (TDNN) into a neurocomputer called EMIND-II with the wavefront toroidal mesh-array structure. The authors also define the programming model of this array and derive the parallel algorithms concerning the TDNN for the EMIND-II. For demonstration purposes, this neurocomputer is applied to word recognition.

Inspec keywords: speech recognition; neural net architecture; parallel algorithms; parallel architectures; parallel machines; delays

Other keywords: wavefront toroidal mesh-array structure; neurocomputer; programming model; EMIND-II; time-delay neural network; parallel algorithms; word recognition application

Subjects: Speech and audio signal processing; Neural net devices; Neural nets (circuit implementations); Speech processing techniques; Neural computing techniques; Parallel architecture; Parallel programming; Microprocessors and microcomputers; Parallel programming and algorithm theory; Speech recognition and synthesis equipment

References

    1. 1)
      • K.J. Lang , A.H. Waibel , G.E. Hinton . A time-delay neural network architecture for isolated word recognition. Neural Netw. , 1 , 32 - 43
    2. 2)
      • Kim, M.W., Kim, J.M., Song, Y.S., Lee, Y.J., Lee, H.B.: `An asynchronous inter-processor communication based, input recyclingparallel architecture', Proc. World Conf. Neural Networks, 1994, p. 576–583.
    3. 3)
      • D. Hammerstrom . Neural networks at work. IEEE Spectrum , 26 - 32
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960159
Loading

Related content

content/journals/10.1049/el_19960159
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading