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Four quadrant analogue CMOS multiplier using capacitively coupled dual-gate transistors

Four quadrant analogue CMOS multiplier using capacitively coupled dual-gate transistors

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Published

A small area, wide dynamic range, four quadrant analogue CMOS multiplier is presented, based on capacitively coupled dual-gate (CCDG) MOSFETs. Models are developed, and the multiplier is simulated with these models. The properties and advantages of the CCDG MOSFET in multipliers are shown, also by comparison with an existing multiplier.

Inspec keywords: CMOS analogue integrated circuits; analogue multipliers; MOSFET circuits

Other keywords: four quadrant analogue CMOS multiplier; dynamic range; model; simulation; CCDG MOSFETs; capacitively coupled dual-gate transistors

Subjects: CMOS integrated circuits; Analogue processing circuits

References

    1. 1)
      • R.M. Barsan . Subthreshold current of dual-gate MOSFETs. IEEE Trans. , 10 , 1516 - 1521
    2. 2)
      • N. Saxena , J. Clark . A four-quadrant CMOS analog multiplier for analog neural networks. IEEE J. Solid-State Circuits , 6 , 746 - 749
    3. 3)
      • H. Fu , J.A. Cooper . Steady-state modelling of resistive-gate MOSFETs. IEEE Trans. , 7 , 1263 - 1269
    4. 4)
      • P. Kinget , M.S.J. Steyaert . A programmable analog cellular neural network CMOS chip for high speedimage processing. IEEE J. Solid-State Circuits , 3 , 235 - 243
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