A current-mode sense amplifier, operating at 622 MHz, in a 0.8 µm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing.
References
-
-
1)
-
M. Afgahi ,
C. Svensson
.
A unified single-phase clocking scheme for VLSI systems.
IEEE J. Solid- State Circuits
,
1 ,
225 -
233
-
2)
-
D.W. Dobberpuhl ,
R.T. Witek ,
R. Allmon ,
R. Anglin ,
D. Bertucci ,
S. Britton ,
L. Chao ,
R.A. Conrad ,
D.E. Dever ,
B. Gieseke ,
S.M.N. Hassoun ,
G.W. Hoeppner ,
K. Kuchler ,
M. Ladd ,
B.M. Leary ,
L. Madden ,
E.J. McLellan ,
D.R. Meyer ,
J. Montanaro ,
D.A. Priore ,
V. Rajagopalan ,
S. Samudrala ,
S. Santhanam
.
A 200-MHz 64-b Dual-Issue CMOS Microprocessor,".
IEEE J. Solid- State Circuits
,
11 ,
1555 -
1567
-
3)
-
K. Seno ,
K. Knorpp ,
L.-L. Shu ,
N. Teshima ,
H. Kihara ,
H. Sato ,
F. Miyaji ,
M. Takeda ,
M. Sasaki ,
Y. Tomo ,
P.T. Chuang ,
K. Kobayashi
.
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier.
IEEE J. Solid- State Circuits
,
11 ,
1119 -
1124
-
4)
-
T.N. Blalock ,
R.C. Jaeger
.
A high-speed clamped bit-line current-mode sense amplifier.
IEEE J. Solid- State Circuits
,
4 ,
542 -
548
-
5)
-
J. Yuan ,
C. Svensson
.
High-speed CMOS circuit technique.
IEEE J. Solid- State Circuits
,
1 ,
62 -
70
-
6)
-
E. Seevinck ,
P.J. van Beers ,
H. Ontrop
.
Current-mode techniques for high-speed VLSI circuits with applicationtocurrent sense amplifier for CMOS SRAM.
IEEE J. Solid- State Circuits
,
4 ,
525 -
536
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19960114
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