622 MHz current-mode sense amplifier

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622 MHz current-mode sense amplifier

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A current-mode sense amplifier, operating at 622 MHz, in a 0.8 µm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing.

Inspec keywords: CMOS analogue integrated circuits; differential amplifiers; UHF amplifiers

Other keywords: 622 MHz; precharge timing; TSPC compatible output timing; current-mode sense amplifier; single phase clocking; CMOS process; 0.8 micron; reset mechanism

Subjects: CMOS integrated circuits; Amplifiers

References

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      • T.N. Blalock , R.C. Jaeger . A high-speed clamped bit-line current-mode sense amplifier. IEEE J. Solid- State Circuits , 4 , 542 - 548
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      • J. Yuan , C. Svensson . High-speed CMOS circuit technique. IEEE J. Solid- State Circuits , 1 , 62 - 70
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      • E. Seevinck , P.J. van Beers , H. Ontrop . Current-mode techniques for high-speed VLSI circuits with applicationtocurrent sense amplifier for CMOS SRAM. IEEE J. Solid- State Circuits , 4 , 525 - 536
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