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MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits

MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits

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A new technique for modelling the conductance of an MOS device for the electrical logic simulation (the Elogic algorithm) of CMOS circuits is proposed. The technique is general and applicable to any analytic device current model. The Elogic algorithm allows the representation of a logic transition using a finite number of voltage steps and calculates time for each transition between the adjacent voltage steps. The examples show that the new technique can correctly predict a complete electrical waveform with a large voltage step of 1 V to yield at least an order of magnitude computational time advantage over the circuit simulation.

Inspec keywords: logic CAD; MIS devices; mixed analogue-digital integrated circuits; circuit analysis computing; CMOS integrated circuits; semiconductor device models

Other keywords: conductance modelling; CMOS circuits; logic transition; electrical waveform; voltage step; Elogic algorithm; mixed-mode simulation; electrical logic simulation; MOS device

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; Computer-aided circuit analysis and design; CMOS integrated circuits; Mixed analogue-digital circuits; Semiconductor integrated circuit design, layout, modelling and testing

References

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      • T. Sakurai , A.R. Newton . A simple MOSFET model for circuit analysis. IEEE Electron Device. Lett. , 54 , 887 - 894
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      • Lee, T.K.: `Techniques for efficient and accurate simulation of mixed analog anddigital circuits', 1994, M Eng., .
    3. 3)
      • R.E. Bryant . A survey of switch-level algorithms. IEEE Design Test Comput. , 26 - 40
    4. 4)
      • T. Sakurai , R. Newton . Delay analysis of series-connected MOSFET circuits. IEEE J. Solid-State Circuits , 2 , 122 - 131
    5. 5)
      • R.A. Saleh , A.R. Newton . (1990) Mixed-mode simulation.
    6. 6)
      • Y.H. Kim , S.H. Hwang , A.R. Newton . Electrical-logic simulation and its application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. , 1 , 8 - 22
    7. 7)
      • R.E. Bryant . A switch-level model and simulator for MOS digital systems. IEEE Trans. Comput. , 2 , 160 - 177
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