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High performance GaAs JFET with shallow implanted Cd-gate

High performance GaAs JFET with shallow implanted Cd-gate

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Shallow p+-regions in GaAs, formed by Cd ion implantation, have been used as the gate region for GaAs JFETs. 0.7 µm gate length JFETs demonstrated a transconductance of 165 mS/mm, a saturation current of 130 mA/mm, an ft of 26 GHz, and an fmax of 42 GHz. These frequency metrics are superior to previous Zn-gate JFETs of similar dimensions.

References

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      • J.C. Zolper , A.G. Baca , R.J. Shul , A.J. Howard , D.J. Rieger , M.E. Sherwin , M.L. Lovejoy , H.P. Hjalmarson , B.L. Draper , J.F. Klem , V.M. Hietala . An all-implanted, self-aligned, GaAs JFET with a non-alloyed W/p+-GaAsohmic gate contact. IEEE Trans. , 1078 - 1082
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