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Cofactor packing algorithm for lookup-table based field programmable gate arrays

Cofactor packing algorithm for lookup-table based field programmable gate arrays

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The authors present a new technology mapping algorithm for an LUT-based FPGA. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by cofactor packing. Experimental results show that the proposed method decomposes infeasible nodes in a shorter CPU time with more than 10% reduced number of nodes compared with previous decomposition methods.

Inspec keywords: logic CAD; table lookup; logic arrays; Boolean functions

Other keywords: algebraic cofactoring; field programmable gate arrays; CPU time; cofactor packing algorithm; lookup-table based FPGA; Boolean network decomposition; technology mapping

Subjects: Electronic engineering computing; Computer-aided circuit analysis and design; Logic and switching circuits; Formal logic; Computer-aided logic design; Logic circuits

References

    1. 1)
      • R. Brayton , R. Newton , A. Sangiovanni-Vincentelli , A. Wang . MIS: multi-level interactive logic optimization systems. IEEE Trans. , 1062 - 1081
    2. 2)
      • J.P. Roth , R.M. Karp . Minimization over Boolean graphs. IBM J. Res. Dev.
    3. 3)
      • Francis, R.J.: `A tutorial on logic synthesis for lookup-table based FPGAs', Proc. ICCAD, Nov. 1992, p. 40–47.
    4. 4)
      • Murgai, R., Shenoy, N., Brayton, R.K., Sangiovanni-Vincentelli, A.: `Improved logic synthesis algorithm for table look up architectures', Proc. ICCAD, Nov. 1991, p. 564–567.
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