Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Scarce-state-transition error-trellis decoding of block codes with BPSK signals

Scarce-state-transition error-trellis decoding of block codes with BPSK signals

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

  • Author(s): L.H.C. Lee 1  and  L.W. Lee 2
    • View affiliations
    • Affiliations: 1: School of Mathematics, Physics, Computing and Electronics, Macquarie University, Sydney, Australia
      2: Advanced Research Division, LTC Limited, Central, Hong Kong
  • Source: Volume 30, Issue 14, 7 July 1994, p. 1120 – 1121
    DOI:  10.1049/el:19940803 , Print ISSN 0013-5194, Online ISSN 1350-911X
© IEE
Published

A novel decoding technique for linear block codes with coherent BPSK signals is proposed. The new system has the same error performance as and similar complexity to the conventional trellis decoding of block codes. Like the scarce-state-transition Viterbi decoding of convolutional codes , the proposed system is also well suited for CMOS VLSI implementation and has a lower power consumption.

Inspec keywords: block codes; trellis codes; decoding; error correction codes; phase shift keying; VLSI; CMOS integrated circuits

Other keywords: linear block codes; coherent BPSK signals; CMOS VLSI implementation; error performance; scarce-state-transition error-trellis decoding; power consumption

Subjects: CMOS integrated circuits; Codes

References

    1. 1)
      • J.K. Wolk . Efficient maximum likelihood decoding of linear block codes. IEEE Trans. , 76 - 80
    2. 2)
      • S. Kubota , S. Kato , T. Ishitanil . Novel Viterbi decoder VLSI implementation and its performance. IEEE Trans. , 1170 - 1178
    3. 3)
      • A.J. Viterbi . Error bounds for convolutional codes and an asymptotically optimum decodingalgorithm. IEEE Trans. , 260 - 269
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19940803
Loading

Related content

content/journals/10.1049/el_19940803
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address