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Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs

Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs

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  • Author(s): W. Fikry 1 ; G. Ghibaudo 1 ; M. Dutoit 2
    • View affiliations
    • Affiliations: 1: ENSERG, Laboratoire de Physique des Composants à Semiconducteurs, URA CNRS, Grenoble, France
      2: Institute for Micro- and Optoelectronics, Swiss Federal Institute of Technology, Lausanne, Switzerland
  • Source: Volume 30, Issue 11, 26 May 1994, p. 911 – 912
    DOI:  10.1049/el:19940577 , Print ISSN 0013-5194, Online ISSN 1350-911X
© IEE
Published

A new method for extracting the drain-induced barrier lowering (DIBL) parameter in an MOS transistor is proposed. This method is used to study the influence of temperature on the DIBL effect. It is found that the DIBL parameter is almost independent of temperature between 50 and 300K. This method makes it also possible to recalculate the intrinsic output characteristics that the device would have in the absence of DIBL, and, in turn, to evaluate the intrinsic device saturation parameters.

Inspec keywords: insulated gate field effect transistors; semiconductor device testing

Other keywords: MOS transistor; DIBL effect; deep submicrometre MOSFETs; drain-induced barrier lowering; temperature dependence; intrinsic output characteristics; 50 to 300 K; DIBL parameter; intrinsic device saturation parameters

Subjects: Insulated gate field effect transistors

References

    1. 1)
      • R.R. Troutman . VLSI limitations from drain induced barrier lowering. IEEE Trans. , 383 - 391
    2. 2)
      • J.C.S. Woo , J.D. Plummer . Short channel effects in MOSFETs at liquid nitrogen temperature. IEEE Trans. , 1012 - 1019
    3. 3)
      • S. Chamberlain , S. Ramanan . Drain induced barrier lowering analysis in VLSI MOSFET devices usingtwo dimensional numerical simulations. IEEE Trans. , 1745 - 1753
    4. 4)
      • M.J. Deen , Z.X. Yan . DIBL in short channel NMOS devices at 77 K. IEEE Trans. , 908 - 915
    5. 5)
      • Z.H. Liu , C. Hu , J.H. Huang , T.Y. Chan , M.C. Jeng , P.K. Ko , Y.C. Cheng . Threshold voltage model for deep sub micrometer MOSFETs. IEEE Trans.
    6. 6)
      • T. Grotjohn , B. Hoefflinger . A parametric short channel MOS transistor model for subthreshold andstrong inversion current. IEEE Trans. , 234 - 246
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