380 ps, 9.5 mW Josephson 4 Kbit RAM

Access Full Text

380 ps, 9.5 mW Josephson 4 Kbit RAM

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors have developed a Josephson 4 Kbit RAM with vortex transitional memory cells and resistor coupled drivers. The RAM is fabricated by 1.5 µm Nb technology with approximately 21000 Nb/AlOx/Nb Josephson junctions. 380 ps access time, 98.6% bit yield, and 9.5 mW power dissipation have been experimentally obtained in the 4 Kbit RAM chip.

Inspec keywords: random-access storage; niobium; aluminium compounds; superconducting memory circuits

Other keywords: vortex transitional memory cells; Nb/AlOx/Nb Josephson junctions; power dissipation; 9.5 mW; 1.5 μm Nb technology; Nb-AlO-Nb; access time; RAM chip; Josephson 4 Kbit RAM; 4 kbit; 380 ps; resistor coupled drivers

Subjects: Memory circuits; Superconducting junction devices; Other digital storage

References

    1. 1)
      • S. Nagasawa , Y. Wada , M. Hidaka , H. Tsuge , I. Ishida , S. Tahara . 570 ps 13 mW Josephson 1-Kbit NDRO RAM. IEEE J. Solid-State Circuits , 1363 - 1371
    2. 2)
      • S. Tahara , I. Ishida , Y. Ajisawa , Y. Wada . Experimental vortex transitional nondestructive read-out Josephson memorycell. J. Appl. Phys. , 851 - 856
    3. 3)
      • I. Kurosawa , H. Nakagawa , S. Kousaka , M. Aoyagi , S. Takada . A 1-Kbit Josephson random access memory using variable threshold cells. IEEE J. Solid-State Circuits , 1034 - 1040
    4. 4)
      • S. Tahara , I. Ishida , S. Nagasawa , M. Hidaka , H. Tsuge , Y. Wada . 4-Kbit Josephson nondestructive read-out RAM operated at 580psec and6.7mW. IEEE Trans. , 2626 - 2633
    5. 5)
      • H. Suzuki , N. Fujimaki , H. Tamura , T. Imamura , S. Hasuo . A 4K Josephson memory. IEEE Trans. , 783 - 788
    6. 6)
      • Nagasawa, S., Hashimoto, Y., Tsuchida, S., Numata, H., Tahara, S.: `Resistor-coupled Josephson polarity-convertible driver', Proc. 1993 IEICE Fall Conf., 1993, p. 5–171, in Japanese.
    7. 7)
      • P.F. Yuh . A 2-Kbit superconducting memory chip. IEEE Trans. Appl. Superconductivity , 3013 - 3021
    8. 8)
      • Numata, H., Nagasawa, S., Tahara, S.: `Fabrication process for sub-micron Josephson junctions', Extended Abstracts of ISEC'93, 1993, p. 280–281.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19940535
Loading

Related content

content/journals/10.1049/el_19940535
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading