20 Gbit/s DR based timing recovery circuit

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20 Gbit/s DR based timing recovery circuit

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Published

The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates.

Inspec keywords: digital communication systems; timing circuits; passive filters; optical receivers; dielectric resonators

Other keywords: optical fibre links; high bit rates; clock recovery unit; narrowband filter; 20 Gbit/s; timing recovery circuit; DR based circuit; open loop structure; RACE 2011 project; dielectric resonator; jitter; clock extraction

Subjects: Passive filters and other passive networks; Other dielectric applications and devices; Optical communication

References

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      • L.E. Franks , J.P. Bubrouski . Statistical properties of timing jitter in a PAM timing recovery scheme. IEEE Trans. , 913 - 920
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      • Y. Imai , E. Sano , M. Nakamura , N. Ishihara , H. Kikuchi , T. Ono . Design and performance of clock-recovery GaAs ICs for high-speed opticalcommunication systems. IEEE Trans. , 5 , 745 - 751
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      • P. Monteiro , J.N. Matos , A. Gameiro , J.R.F. da Rocha . 10 Gbit/s timing recovery circuit using dielectric resonator and activebandpass filter. Electron. Lett. , 9 , 819 - 820
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      • Matos, J.N., Monteiro, P., Gameiro, A., da Rocha, J.R.F.: `Bit synchronisation in multigigabit receivers', SPIE Proc., 1993, 1974, Berlin, p. 148–159.
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