An n-step charge injection cancellation scheme for switched current (SI) circuits is presented. By modifying a recently proposed two-step SI cell so that fine memories can be cascaded, n-stage fine cell schemes are now possible. The technique has been applied to CMOS class A, class AB and GaAs class A second generation cells.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el_19940486
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content/journals/10.1049/el_19940486
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