Minimum memory buffers in DSP applications

Minimum memory buffers in DSP applications

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The authors compute the minimum required buffer sizes that still guarantee the construction of a deadlock-free static schedule in synchronous multirate data flow graphs. The results are applicable to the rapid prototyping of DSP algorithms.


    1. 1)
      • J. Pino , S. Ha , E.A. Lee , J. Buck . Software synthesis for DSP using Ptolemy. J. VLSI Signal Process.
    2. 2)
      • M. Engels , R. Lauwereins , J.A. Peperstraete . Rapid prototyping for DSP systems with multiprocessors. IEEE D&T of Comp. , 2 , 52 - 62
    3. 3)
      • Note, S., Vandebroeck, P., Odent, P., Genin, D., and VanCanneyt, M.,Top down design of two industrial IC's with DSP station,DSP Applications,1993.
    4. 4)
      • Signal Processing Worksystem (SPW™) Manuals,Comdisco Systems, Inc..
    5. 5)
      • Dennis, J.B.: `The varities of data flow computers', Proc. first Int. Conf. on Distributed Computer Systems, 1979, p. 430–439.
    6. 6)
      • E.A. Lee , D.G. Messerschmitt . Static scheduling of synchronous data flow programs for digital signalprocessing. IEEE Trans. , 1 , 24 - 35
    7. 7)
      • E.A. Lee , D.G. Messerschmitt . Synchronous data flow. Proc. IEEE , 9 , 1235 - 1245

Related content

This is a required field
Please enter a valid email address