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An ECL gate implemented as a combination of bipolar and MOS circuits in a BiFET process is presented. The resulting ECL gate exhibits an improved speed-power product over circuits presented in the past. Owing to its reduced power consumption this gate allows a higher level of integration for ECL. The process used is standard BiCMOS.
References
-
-
1)
-
C.T. Chuang
.
Advanced bipolar circuits.
IEEE Circuits and Devices Magazine
,
6 ,
32 -
36
-
2)
-
C.T. Chuang
.
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage.
IEEE J. Solid-State Circuits
,
8
-
3)
-
C.T. Chuang
.
High-speed low-power AC-coupled complementary push-pull ECL circuit.
IEEE J. Solid-State Circuits
,
4
-
4)
-
Shin, H.J.: `Self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits', 1993 Symp. on VLSI Circuits, Dig. Technical Papers, 19–21 May 1993, Kyoto, Japan, p. 27.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19931354
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