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CMOS driver for 50 Ω load

CMOS driver for 50 Ω load

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© The Institution of Electrical Engineers
Published

A new CMOS output driver with ECL-level interface has been designed. The output stage, using a pMOS transistor, is designed for low power dissipation. A data rate in excess of 700 Mbit/s has been achieved in a 1.2 μm process.

Inspec keywords: emitter-coupled logic; integrated logic circuits; CMOS integrated circuits; driver circuits

Other keywords: CMOS driver; 50 ohm; output stage; ECL-level interface; 700 Mbit/s; 1.2 micron; low power dissipation

Subjects: Logic circuits; CMOS integrated circuits; Logic and switching circuits

References

    1. 1)
      • H.-J. Schumacher , J. Dikken , E. Seevinck . CMOS sub-nanosecond true ECL output buffer. IEEE J. Solid-State Circuits
    2. 2)
      • Ishibashi, K.: `A 1.7 V adjustable I/O interface for low voltage fast SRAMS', Tech. Dig. '91 VLSI Circuit Symp, May 1991, p. 97.
    3. 3)
      • Gabara, T.J., Thompson, D.W.: `A 200 MHz ECL output buffer for CMOS ASICS', Third Annual IEEE ASIC Seminar and Exhibit, 17th–21st September 1990.
    4. 4)
      • Steyaert, M., Bijker, W., Vorenkamp, P., Sevenhans, J.: `A full 1.2 μm CMOS ECL-CMOS-ECL converter with subnanosecond settling times', IEEE Custom Integrated Circuit Conf., 1990.
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