Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology

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Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology

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© The Institution of Electrical Engineers
Published

Floating gate MOSFET structures were fabricated in a standard 2 μn double-polysilicon CMOS process which requires programming voltages of only 6.5–9V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.

Inspec keywords: CMOS integrated circuits; analogue storage; VLSI

Other keywords: interpolysilicon oxide; capacitive geometries; analogue memory cells; 6.5 to 9 V; VLSI CMOS technology; double-polysilicon CMOS process; programming voltages; tunnelling; 2 micron; floating gate

Subjects: Analogue processing circuits; Analogue storage; CMOS integrated circuits

References

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      • D.A. Durfee , F.S. Shoucair . Comparison of floating gate neural network memories in standard VLSI CMOS technologies. IEEE Trans. Neural Netw. , 347 - 353
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      • A. Thomsen , M.A. Brooke . A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process. IEEE Electron Device Lett. , 111 - 113
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      • B.W. Lee , B.J. Sheu , H. Yang . Analog floating-gate synapses for general-purpose VLSI neural computation. IEEE Trans. , 654 - 658
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      • L.R. Carley . Trimming analog circuits using floating gate analog MOS memory. IEEE J. Solid-State Circuits , 1569 - 1575
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