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Lower bound of sample word length in bit/digit serial architectures

Lower bound of sample word length in bit/digit serial architectures

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© The Institution of Electrical Engineers
Published

In bit/digit-serial architectures the allowable sample word length is lower-bounded to synchronise the feedback loops (the cycles) correctly. A systematic procedure for finding this lower bound and the critical cycle that achieves the bound are described. From this information a successful schedule can be guaranteed for all cases, which has been difficult using previous approaches.

Inspec keywords: VLSI; computer architecture; digital signal processing chips

Other keywords: bit/digit serial architectures; critical cycle; schedule; feedback loops; systematic procedure; sample word length

Subjects: Microprocessors and microcomputers; Semiconductor integrated circuits; Computer architecture; Digital signal processing chips

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