Dynamic latch for high speed GaAs domino circuits

Dynamic latch for high speed GaAs domino circuits

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A latch for use with GaAs domino logic gates is presented. A hybrid of a GaAs domino logic gate and a two-phase dynamic FET logic gate, the latch stores data during the precharge phase of domino logic operation. It enables the use of domino logic in large scale systems without the need for interfacing with power consumptive static latches. It is implemented with depletion mode MESFETs and dissipates 0.8 mW.


    1. 1)
      • L. Yang , R. Chakharapani , S.I. Long . A high speed domino circuit implemented with GaAs MESFE's. IEEE J. Solid-State Circuits , 874 - 879
    2. 2)
      • D.H.K. Hoe , C.A.T. Salama . Dynamic GaAs capacitively coupled domino logic (CCDL). IEEE J. Solid-State Circuits , 844 - 849
    3. 3)
      • Nary, K.R., Long, S.I.: `Two-phase dynamic FET logic: an extremely low power, high speed logic family for GaAs VLSI', IEEE GaAs IC Symp. Tech. Dig., 1991.
    4. 4)
      • Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, CA 90292.

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