Second substrate current peak and its relationship to gate-voltage dependent series resistance in submicrometre nMOS LDD

Second substrate current peak and its relationship to gate-voltage dependent series resistance in submicrometre nMOS LDD

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The occurrence of the second substrate current hump (SSCH) has been thoroughly investigated [1, 2, 3] and it is well known that the lateral electric field at the source sid4e (E5) is responsible for the appearance of the SSCH in sub-micrometre nMOS LDD transistors. However the fall off of the SSCH after reaching in maximum value. the so called second substrate current peak (SSCP), is not well understood and explained. In the Letter and improved model of the lateral electric field at the source side, which explains the SSCP in terms of the dependence of the source resistance Ris on the gate-source voltage, is introduced.


    1. 1)
      • J. Hui , F.C. Hsu , J. Moll . A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices. IEEE Electron Device Lett. , 3 , 135 - 138
    2. 2)
      • T.Y. Chan , A.T. Wu , P.K. Ko , C. Hu , R.R. Razouk . Asymmetrical characteristics in LDD and minimum-overlap MOSFETs. IEEE Electron Device Lett. , 1 , 16 - 19
    3. 3)
      • M. Orlowski , C. Werner , J.P. Klink . Model for the electric fields in LDD MOSFET's-Part I: field peaks on the source side. IEEE Trans. , 2 , 375 - 381
    4. 4)
      • Gutierrez-D., E.A., Deferm, L., Declerck, G.: `Temperature dependence of the electric field at the source side and its influence on the overall substrate current behavior of submicron NMOS transistors', Proc. 179th Meeting of Electrochemical Society Symp. on Low Temperature Electronic Device Operation, May 1991, Washington DC, To be published in.
    5. 5)
      • E.A. Gutierrbz-D. , L. Deferm , G. Declerck . (1991) Trans-conductance degradation and its correlation to the second substrate current hump of submicron NMOS LDD transistors, Microelectronics engineering.
    6. 6)
      • B.T. Murphy . Unified field-effect transistor theory including velocity saturation. IEEE J. Solid-State Circuits , 3 , 325 - 328
    7. 7)
      • F.M. Klaassen . A MOS model for computer-aided design. Philips Res. Rep. , 71 - 83

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